1. Field of the Invention
The present invention relates to the transmission of digital data characters in parallel data slices, and in particular, to a technique for improving bus transfer rates by allowing an individual data slice and its associated clock signal to flow through the same data path, thereby reducing skew.
2. Discussion of the Prior Art
Referring to FIG. 1, a conventional system for transmitting data characters over a bus in multiple parallel data slices typically utilizes transceiver devices connected to the bus for transferring the data characters to and from the bus. According to conventional bus interface architecture, each module on a plug-in board includes a number of separate, parallel-configured, integrated circuit memory chips, such as slice-wide first-in-first-out (FIFO) memory devices of a desired depth, each of which serves as either a "transmitter" or "receiver" storage device for a data slice path. Each "transmitter" memory chip utilizes a separate, dedicated transmitter unit bus driver chip to sequentially pass data slices from its associated memory chip to the bus. Similarly, each "receiver" memory chip utilizes a separate, dedicated receiver unit bus receiver chip to sequentially pass data slices from the bus to its associated receiver memory device.
For example, to implement the transmission of a 32-bit data character, i.e. doubleword data, each of four 8-bit wide transmitter FIFO chips provides a data path for transferring byte-wide data slices through four associated bus driver chips to the data bus for capture by a similarly configured receiver arrangement.
The use of this conventional data path configuration requires external control logic to implement the protocol for data transfers. That is, a separate logic chip implements the bus protocol for the transmission.
The disadvantage of this design is that the timing of the data path for each data slice and for the protocol logic of the control path are on separate integrated circuit chips, thereby introducing skew in the received data. Typically, the propagation delay through conventional integrated circuit devices used in these applications, based on process variation, temperature variation and V.sub.cc variation, ranges from a minimum of 1 nsec. to a maximum of 7 nsec. Thus, each of the four chips comprising each data slice path, i.e., transmitter memory, bus driver, bus receiver and receiver memory, can introduce up to a 6 nsec. propagation delay difference in the parallel data slice paths.
These skew effects severely limit performance. Since one control strobe is used as the common clock for all of the data path elements, the transfer rate for each data character must be assumed to be limited by the worst case propogation delay for each device. Thus, as shown in FIG. 1, in the typical case, a skew delay of 24 nsec. must be built into the receiver unit to ensure that the control strobe arrives after the received data is valid. This limits data transfer rates to about 40 million transfers per second.